1. Field
The embodiments discussed herein relate to a PLL circuit and a method for operating a PLL circuit.
2. Description of Related Art
Analog circuits are being replaced with digital circuits due to an increase in electric currents, an increase in circuit areas or variances in characteristics, for example. As an operation voltage of a semiconductor circuit reduces, a dynamic range of an Analog to Digital Converter (ADC) may be reduced. An All Digital Phase-Locked Loop (ADPLL) circuit which uses a Time to Digital Converter (TDC) for discretizing time may be provided.
Related art is disclosed in Japanese Unexamined Patent Application Publication No. 2002-76886 or 2009-268047, etc.